1. Field of the Invention
The invention relates to a method for forming a crystalline silicon layer and a crystalline silicon semiconductor device, and more particularly to a method for forming a crystalline silicon layer which can form an evenly oriented, high-quality polycrystalline or single-crystal silicon layer in a large area, and a crystalline silicon semiconductor device produced by said method.
2. Prior Art
Elements comprising a crystalline silicon layer grown on a foreign substrate are known as a material suitable for semiconductor devices such as solar cells and semiconductor elements on SOI (silicon on insulator). Semiconductor devices using these elements do not require a large-area, high-quality silicon crystal substrate and thus are advantageous in that a significant reduction in cost can be expected and, in addition, by virtue of the absence of the silicon substrate, an increase in speed of circuit operation can be expected.
In general, in order to provide excellent properties in this type of semiconductor devices, the quality of the crystalline silicon layer to be formed should be enhanced. Therefore, the use of heat-resistant but expensive substrates, such as quartz which can withstand high temperatures, is indispensable. This generally poses a problem of a limitation on cost reduction due to the use of expensive substrates.
In order to solve this problem, a method has been proposed which comprises melt crystallizing an amorphous silicon layer grown on a substrate, for example, by laser annealing to form a crystalline silicon layer on the substrate. This method is disclosed in K. Yamamoto et al., 1994 IEEE First World Conference on Photovoltaic Energy Conversion (Hawaii in 1994) pp. 1575-1578. This method is described to suppress a temperature rise of the substrate and thus to realize the use of low-cost substrates.
According to this method, however, the diameter of crystal grains, which can be formed, is about 1 xcexcm, and, thus, the crystals as such cannot be put to practical use. In recent years, crystals having a larger diameter could have become produced, and, for example, the production of crystals having a size exceeding 100 xcexcm has been reported. The production of crystals having a size exceeding 1 cm square, however, has not been reported yet. Therefore, evenly forming a crystal over the whole area of a substrate having a size exceeding 30 cm is utterly impossible to realize. Further, there is an additional problem that a crystal region having a small grain diameter is formed around the crystal formed by this method. For this reason, it should be said that the method reported in the above literature cannot be put to practical use without difficulty.
In order to advantageously grow a crystalline silicon layer, R. C. Cammarata et al. have proposed a method which comprises the steps of: bringing a metal catalyst into contact with amorphous silicon; and, in this state, performing heat treatment to crystallize the amorphous silicon layer [J. Mater. Res., Vol. 5, No. 10 (1990) pp. 2133-2138]. This method is described as a method which can form a crystalline silicon layer at a low temperature and at a high speed and, in particular, crystallization at a low temperature can be achieved, for example, by introducing a very small amount of a nickel metal and then performing heat treatment.
L. K. Lam et al. have confirmed that, according to this method, when the object is a thin film having a thickness of about 100 nm, such as a TFT element, the crystallization advances in an in-plane direction by several xcexcm and, thus, a high-quality crystal having good orientation in the in-plane direction can be obtained [Appl. Phys. Lett., Vol. 74, No. 13 (1999) pp. 1866-1868]. Further, a method for enhancing performance has been proposed, as a method utilizing growth with orientation, wherein a metal catalyst is selectively disposed near the position of a TFT element and, in this state, heat treatment is carried out to crystallize amorphous silicon, whereby an element is formed within crystal grains (Japanese Patent Laid-Open No. 244104/1994).
The above conventional methods, however, cannot produce semiconductor devices for solar cells and the like. Specifically, although the convention methods could be successfully applied to TFT elements of which the crystal area is about 100 xcexcm, in the case of solar cells or semiconductor devices is about such as integrated circuits, a high-quality crystal should be grown over substantially the whole area of the substrate. This cannot be realized by the conventional methods.
Accordingly, it is an object of the invention to provide a method for forming an evenly oriented high-quality crystalline silicon layer in a large area, and to provide a crystalline silicon semiconductor device produced by said method.
According to the first feature of the invention, a method for forming a crystalline silicon layer, comprises the steps of: forming an amorphous silicon layer on a substrate; heat treating the amorphous silicon layer in the presence of a catalytic metal element to crystallize the amorphous silicon layer, wherein
a plurality of linear catalytic metal element portions are arranged at predetermined intervals just on or just beneath the amorphous silicon layer formed on the substrate, and
the amorphous silicon layer is heat treated to crystallize the amorphous silicon layer in the presence of the linear catalytic metal element portions to form a crystalline silicon layer.
According to the second feature of the invention, a crystalline silicon semiconductor device comprises: a substrate; a laminate comprised of crystalline silicon layers; and an electrode provided at a predetermined position,
said crystalline silicon layer having been formed by heat treating an amorphous silicon layer just on or just beneath which a plurality of linear catalytic metal element portions have been arranged at predetermined intervals.
Preferably, from the viewpoint of ensuring the formation of a crystalline silicon layer over the whole area of the substrate, the liner catalytic metal element portions are arranged so as to spread over the whole area or substantially the whole area of the substrate. The intervals of the catalytic metal element portions are, for example, several hundred xcexcm to several mm which is useful for the crystallization of the amorphous silicon layer on the whole area of the surface of the substrate.
Therefore, the amorphous silicon layer, just on or just beneath which the catalytic metal element portions have been arranged, can be crystallized so as to highly conform to any area of the substrate by the provision of linear catalytic metal element portions without any particular limitation on the number of linear catalytic metal element portions arranged and by properly setting the intervals of the linear catalytic metal element portions. As a result, the formation of an oriented crystalline layer having a large area, which has been difficult to realize in the prior art, can be easily realized.
The linear catalytic metal element portions are in many cases in the form of lines or strips having an identical width and are generally linearly arranged. However, if necessary, for example, the width of the linear catalytic metal element portion may be changed between both ends thereof, or the linear catalytic metal element portion may be bent between both ends thereof.
The step of arranging the linear catalytic metal element portions just beneath the amorphous silicon layer is preferably carried out in such a manner that grooves are formed on the surface of the substrate and filled with the catalytic metal element and the amorphous silicon layer is then formed on the substrate. In this case, a method is generally adopted which comprises the steps of: coating a solution of a catalytic metal element; wiping off the solution present on the outside of the grooves; and then drying the coated catalytic metal element solution to leave the catalytic metal element within the grooves. Since the catalytic metal element is received in the grooves, the surface of the substrate is smooth. This can avoid the formation of local protrusions of the catalytic metal element on the amorphous silicon layer formed on the substrate.
According to a preferred embodiment, the adoption of the following method is recommended. A plurality of amorphous silicon layers having a shape such as a strip are juxtaposed, and, in addition, a liner catalytic metal element portion is disposed just on or just beneath one end of each of the amorphous silicon layers. In this state, heat treatment is carried out. According to this method, the portion containing a high concentration of a catalytic metal element in the formed crystalline silicon layer can be provided in a portion which is not the center of each of the crystalline silicon layers, preferably at an end opposite to the end where the catalytic metal element has been disposed. This permits the catalytic metal element to be concentrated on that portion. Therefore, whereas, when the catalytic metal element has been provided at the center portion of the silicon layer, excessive heat treatment causes the portion containing a high concentration of the catalytic metal element located at the center portion to be spread by diffusion, the above structure involves this problem.
Catalytic metal elements include nickel, iron, cobalt, platinum, copper, and gold.
The amorphous silicon layer preferably has a dopant concentration in the range of a low concentration, which is on a substantially i type level, to 2xc3x971020/cm3. When the dopant concentration falls within this concentration range, both the quality of the resultant crystal can be improved and, in addition, the crystallization speed can be increased. Materials for constituting the amorphous silicon layer usable herein include silicon, silicon hydride, halogen-containing silicons, and silicon-base compounds or alloys, such as SiC, SiN, SiO, and SiGe. In particular, when, in Si1-xGex, X is set to not more than 0.3, that is, so as to provide a low germanium concentration region, a good crystallization acceleration effect can be provided. In particular, when a laminate comprising germanium placed on nickel is used, two elements exhibit synergistic effect. As a result, crystallization can proceed at a high speed. Thus, an advantage of efficiency can be attained. Further, according to this embodiment, the produced polycrystalline silicon layer consists essentially of silicon crystal. Therefore, a high-quality crystalline silicon layer can be formed.
The heat treatment for the transformation of the amorphous silicon layer to the crystalline silicon layer is preferably carried out in the temperature range of 450 to 700xc2x0 C., more preferably in the temperature range of 500 to 650xc2x0 C. The heat treatment is preferably carried out in a nitrogen, hydrogen, argon, or halogen atmosphere or in vacuo.
Among others, heating, for example, to 400xc2x0 C. in a hydrogen atmosphere to form a silicide or to reduce the amount of hydrogen contained in the layer followed by heating, for example, to about 550xc2x0 C. results in the formation of a crystalline silicon layer having particularly good orientation.
A portion with a high catalytic metal element concentration corresponding to the portion, where the linear catalytic metal element portion has been located, and a portion with a low catalytic metal element concentration corresponding to a position intermediate between the catalytic metal element portions are formed in the crystalline silicon layer. These portions have substantially no influence on the characteristics of the semiconductor device. However, regarding these catalytic metal element-containing portions, when more strict control is required, the step of removing these portions is sometimes additionally provided.
The formation of other crystalline silicon layer on the polycrystalline or single-crystal silicon layer formed according to the invention to thereby form a predetermined epitaxial layer as a semiconductor device is embraced, as an extension of the above-described matter, within the embodiment of the invention. According to the invention, this embodiment can reduce the concentration of the catalytic metal element included in the other crystalline silicon layer to a low level of not more than 1xc3x971017/cm3. This level can be mentioned as one feature of the semiconductor device produced by the invention.
Materials for constituting the substrate used in the invention include, for example, inorganic materials, such as glass, sapphire, and ceramics, or metallic materials, such as SUS, molybdenum, and tungsten. The formation of a crystalline silicon layer on silicon oxide, a nitride film, a metal film for an electrode, or a conductive film, such as a zinc oxide film, poses no problem.
Further, in the semiconductor device according to the invention, the position of the electrode provided on the upper side of the crystalline silicon layer may vary depending upon the type and construction of the semiconductor device. For example, the electrode may be provided just on the crystalline silicon layer formed according to the invention or on other layer formed on the crystalline silicon layer.